The miniaturizing of systems utilizing complex integrated circuits has required that increasingly complex circuitry be imprinted on chips of decreasing size. This reduction in size, or increase in volumetric capacity, has reached the point where the techniques available to the industry have been stretched to the limit of their capabilities. As it is, the yield of the most advanced integrated circuit chips produced by standard techniques is extremely low, on the order of 1%, due to attempts to put more and more capacity into a smaller and smaller volume. At the level of capacity which is being demanded by the industry today, the current photo-lithographic processes cannot produce a complete, workable structure more than about 1% of the time.
The problem is due in a great extent to the limitations of the photographic process used. At the microscopic level which is required, the layers of chip material, silicon, for example, are not perfectly smooth and flat. Moreover, the uneven topography is of a magnitude approximating that of the wave length of the light which is used to form the images in the photoresistive material which is applied to the layers of the chip. The light which is used to image the photoresistive material is reflected from the substrate of the chip material, that is, the silicon wafer. This reflection, coupled with the uneven topography, causes an uneven distribution of light in the imageable material and results in a large number of artifacts being produced in the developed image. These artifacts cause a large number of rejects in any semi-conductor structure built by current techniques.
It is apparent that if artifacts can be eliminated or reduced the yield of integrated circuit chips can be increased resulting in great efficiency and reducing the cost of producing such materials.
Recently there have been a number of attempts to reduce the artifacts caused by reflected light. U.S. Pat. No. 4,102,683, the disclosure of which is incorporated herein, discusses one such attempt. Other discussions appear in the IEEE Transactions on Electron Devices, Edition 28, No. 11 of Nov. 1981, pages 1405 through 1410, entitled "Line Width Control and Projection Lithography Using a Multi-Layer Resist Process" by O'Toole, et al. and in "Reduction of the Standing Wave Effect in Positive Photo-Resist," Brewer, et al. in Journal of Applied Photographic Engineering, Vol. 7, No. 6, Dec. 1981, pages 184 through 186, and "Control of One-Micron Lines in Integrated Circuits," Carlson, el al., Kodak, '80 Interface, Oct. 1980, pages 109 through 113.
Applicant has discovered an improved photolithographic process for integrated circuits, an improved anti-reflective material for use therein and an integrated circuit chip utilizing such material. Applicants'process uses an anti-reflective coating that eliminates deleterious effects due to internal reflections from wafer surfaces and photoresist surfaces. Applicants'material offers better adhesion, greater light absorption, is a thinner, more uniform coating, and has a more controlled development and requires fewer process steps than those previously known. Applicants' material is compatible with and images with the photoresist, in the integrated circuit manufacturing process. Applicants'coating leaves less residue on the integrated circuit wafers after development.